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8
Available Options
AV-51001
2013.12.26
Available Options
Figure 2: Sample Ordering Code and Available Options for Arria V GT Devices
Embedded Hard IPs
M : 1 hard PCIe and 2 hard
Transceiver Count
Maximum channels
D : 9
Package Type
F : FineLine BGA (FBGA)
memory controllers
G
:
18
Operating Temperature
F : 2 hard PCIe and 4 hard
memory controllers
H
K
:
:
24
36
I
: Industrial (T J = -40° C to 100° C)
Family Signature
5A : Arria V
5A
GT
F
D7
K
3
F
40
I
3
N
Optional Suffix
Indicates specific device
Family Variant
Package Code
options or shipment method
N : Lead-free packaging
GT : 10-Gbps transceivers
Member Code
C3 : 156K logic elements
C7 : 242K logic elements
D3 : 362K logic elements
D7 : 504K logic elements
Transceiver
Speed Grade
3 : 10.3125 Gbps
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
40 : 1,517 pins
Contact Altera for availability
of leaded options
ES : Engineering sample
FPGA Fabric
Speed Grade
3 (fastest)
5
Maximum Resources
Table 6: Maximum Resource Counts for Arria V GT Devices
Resource
Logic Elements (LE) (K)
ALM
Register
C3
156
58,900
235,600
C7
242
91,680
366,720
Member Code
D3
362
136,880
547,520
D7
504
190,240
760,960
Memory (Kb)
M10K
MLAB
10,510
961
13,660
1,448
17,260
2,098
24,140
2,906
Variable-precision DSP Block
18 x 18 Multiplier
PLL
396
792
10
800
1,600
12
1,045
2,090
12
1,156
2,312
16
Transceiver
GPIO (6)
6 Gbps (4)
10 Gbps (5)
3 (9)
4
416
6 (24)
12
544
6 (24)
12
704
6 (36)
20
704
(4)
(5)
(6)
The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10 Gbps
channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets.
Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture
in Arria V Devices chapter.
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
Altera Corporation
Arria V Device Overview
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